This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-023369, filed Jan. 31, 2001; and No. 2001-395241, filed Dec. 26, 2001, the entire contents of both of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a high voltage semiconductor device, for example, an IGBT (Insulating Gate Bipolar Transistor).
2. Description of the Related Art
Technologies relating to IGBTs have been considerably developed. In the last ten years, decrease in ON-voltage and increase in switching speed have been advanced significantly. For example, IGBTs of the 600V series have been developed, in which the current fall time is 100 ns, the current density is 150 A/cm2 and the ON voltage is 1.8V or lower. However, there is an increasing demand for a lower ON voltage and a higher switching speed. Further, as the switching speed is increased, decrease in noise is also required.
Use of a trench gate and a thin wafer is known as a technique for lowering the ON voltage.
FIG. 19 shows an example of the general IGBT of the 600V series. This IGBT has a non punch-through structure using no n+ buffer layer. It comprises a p+ drain layer 101, an about 100 xcexcm thick nxe2x88x92 high resistance layer 102, a p base layer 103, a source region 104 and a trench gate electrode 105. In this IGBT, since an anode injected with a small amount of impurities is formed of the thin drain layer 101, the switching speed can be increased without controlling the lifetime of the high resistance layer 102.
FIG. 20 shows another example of the IGBT. Like reference numerals denote the same parts as those shown in FIG. 19. The IGBT has a punch-through structure using an n+ buffer layer 106. The n+ buffer layer 106 and a high resistance layer 102 are formed on a p+ substrate 107 by epitaxial growth. The punch-through IGBT is produced by using the p+ substrate 107, which is relatively thick. Therefore, to lower the efficiency of implantation from a drain layer 101 to the high resistance layer 102, the n+buffer layer 106 of a high impurity concentration is used and the wafer is subjected to annealing by irradiation with an electron beam after completion of the wafer process. With the above structure, the lifetime can be reduced, thereby increasing the switching speed.
In the case of the punch-through IGBT, since the n+ buffer layer 106 is used, the high resistance layer 102 can be thin. In the IGBT of the 600V series, the thickness of the high resistance layer 102 is about 50 xcexcm for example. In the punch-through IGBT, the thickness of the p+ substrate 107 is not particularly important but can be handled in the wafer process. To be specific, the substrate 107 is 500 to 600 xcexcm thick.
As described above, the punch-through structure is suitable for lowering the ON voltage. However, the punch-through IGBT has the following problems.
(1) To increase the switching speed, the lifetime should be shortened or the efficiency of implantation to the p+ drain layer 101 should be reduced. However, since the thick p+ substrate is used in the punch-through IGBT, it is difficult to reduce the total amount of impurities in the drain layer 101 to lower the hole implantation efficiency. Therefore, the lifetime should inevitably be shortened. However, if the lifetime is shortened, the concentration of carriers in the high resistance layer 102 is lowered. In the case of the punch-through IGBT, since the high-resistance layer 102 is thin, the voltage drop of the high resistance layer 102 is increased, making it difficult to lower the ON voltage. Consequently, it is not easy to increase the switching speed in the punch-through IGBT.
(2) In the punch-through structure, a depletion layer is formed to extend in the high resistance layer 102 by a voltage applied when the current is turned off. The depletion layer is stopped by the n+ buffer layer 106. For this reason, the drain current is immediately dropped to zero. Therefore, the drain voltage oscillates as shown in FIG. 21, resulting in generation of noise.
Under the circumstances, there is a demand for an IGBT which allows both increase in switching speed and decrease in noise.
According to an aspect of the present invention, there is provided a semiconductor device comprising: a drain layer of a first conductivity type; a buffer layer of a second conductivity type formed above the drain layer; a high resistance layer of the second conductivity type formed on the buffer layer; a base layer of the first conductivity type formed on the high resistance layer; a source layer of the second conductivity type, containing a high concentration of impurities, formed in a surface region of the base layer; a gate electrode formed in the base layer with an insulating film interposed therebetween; and a low concentration layer formed between the drain layer and the buffer layer, an impurity concentration of the low concentration layer being lower than those of the drain layer and the buffer layer.